It is well known that the capacitance of a capacitor device scales with the area of the capacitor electrodes, with the dielectric constant of the dielectric material between the capacitor electrodes, and with the inverse of the distance between the capacitor electrodes.
To increase the area of the capacitor electrodes comprised in electronic devices, which are formed by integrated circuits on a semiconductor chip, trench capacitors have widely been used. In a trench capacitor, the electrodes are formed by electrically conductive layers deposited in a recess or pore prepared in the substrate (wafer). A pore or trench can for instance be made by locally etching the substrate. The production of dense arrays of such features is well known. Electrode layers can be formed in the pores by known deposition techniques, such as low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The electrically conductive layers are electrically isolated from each other and from the substrate by interposed dielectric layers.
A pore filled in this way to form a trench capacitor typically has a general shape resembling the letter “U” in a cross-sectional view. It is known to arrange a large number of pores in a substrate, in the form of a pore array, and to deposit step-conformal, that is, uniformly thick electrode layers in all pores in an attempt to achieve high capacitance values in electronic devices containing trench capacitors. A capacitance density, defined as a capacity value per unit area, is used to characterize such trench capacitor devices. Capacitance density values of about 30 nF/mm2 with a breakdown voltage of 30 V can be achieved using MOS (Metal-Oxide-Semiconductor)/MIS (Metal-Insulator-Metal) capacitor layer stacks grown in pore arrays etched in a high-surface area silicon substrate, see WO2004/114397.